No, I am not. I am stating that Mackey is using the article's context in the
wrong manner. Mackey is talking abuot single bit flipping. The article is
talking abuot BLOCKS of data.
The various articles speak of corrupted data in single and adjacent cells. They refer to tunneling effects and punchthrough that occurs despite the fact that they would not occur IF the transistors were ideal, which is how you are trying to portray them.
Good then, you acknowledge that there would be differences along the line.
Same question to you as presented to Myriad. How far away do you believe
these gates are positioned?
microns
Marco, or Micro. Parallel is parallel. Do I need to draw a circuit to explain this
concept?
No, it is NOT the same. In transient situations the high frequency components of the spike take precedence over the DC functionality of the cct. there is inherent impedance per unit length of cct, and a slightly different impedence to every gate, drain and source connection. So the further from the source of the spike the less the effect, some transistors will have a slightly different impedence than others and be affected differently AND the most affected transistors will be the ones being written to and those that are physically proximate to them.
This is ONE of the reasons that memory systems have specific power down procedures which is one of the things that obviously does not occur when the machine containing that memory is slammed into a concrete wall.
In this scenario, the data would likely be stored as contiguous data and
not fragmented for some sort of security purpose. Near. (Is Grover
going to appear soon?
)
Who said it would be fragmented? Indeed the fact that it is written contiguously would mean that when word (bit, cell)"A" gets stored on the chip it will reside , physically, next to word (bit, cell)"B" and that if something catastrophic happens to "A" then the fact that "B" is right there bodes ill for "B" too.
Well that depends on the IC design. As stated many times, the gates
are tied together. You are talking about single cell state change.
Individuals next to one another will be affected. You really don't seem to be able to grasp that this situation in no way resembles the way the cct was designed to operate and that bad and odd things happen when transients enter the picture.
Nothing, unless you mean the bit/gate that is currently accessed and receiving
a write instruction?
The difference between the two would be address lines enabled (vs. tri-stated), current paths, etc.
Anyone care to explain how just one gate can be altered in such a design.
Wrong, the difference between cells/gates presently being written to, cells written to last and cells written to several minutes ago is that the ones being written to are the most sensitive to transients, the ones physically on the chip proximate to those cells are the cells last written to and are the next most in danger of corruption and the ones written to several minutes ago are physicall on the chip farther away and less in danger of corruption by this transient.
Here's a senario from my experience. It takes place in larger world rather than the micro world of a dense IC but it is useful in understanding that a transient is different than normal operation, to say the least.
I worked on a slow bit rate data line that ran a couple of hundred feet from one building to another. The twisted pair was in a cable that was buried but the location was the arctic, very dry, very static prone. There was fused protection at each end of the line.
One day the line went dead for no apparent reason. I checked the fuse at the send end. It was blown. I replaced it. still no joy. Out to the other building. Data is coming to the building but the fuse at that end is also blown. I replace it but still no joy. I check the terminating equipment and there the input transistor buffer is also no more than a bit of useless carbon inside an intact case(it too was blown).
So tell me TF, how does a transient operate in this single 'bus' such that it can simultaneously vlow three items in series? Should not one blow and then protect the other two given that it is now a huge resistance?
