AA77 FDR Data, Explained

[Jonnyclueless]

All this is is an attempt to focus on a small specific area so as to listen the number of people who are are familiar with it. It's simply a way of saying "unless you understand this enough to make an argument about this specific area, I can then fill in the blanks with anything I want and not be required to provide evidence".

The desire and taunting of a vocal discussion is just to further get the numbers down.

All of this to distract from the unavoidable outcome that can be the only result of the argument. That is that we then have to accept that 1000s of witnesses were all there and just happened to miss a giant airliner flying over the building, and 1000s of people didn't happen to catch the plane being planted at the scene at the moment of impact. And 1000s of people not noticing people planting the broken light poles. And that the NTSB and the FBI, and everyone else in the government would have to be in on it. That the victims family members who talked to people on the plane would have to be in on it. That this big elaborate plan was devised to work on a one in a million chance of being successful. I could go on and on.

All of that, or the FDR lost data as is normal in accidents. And in order to avoid this absurdity, they have to avoid addressing these inevitable outcomes for which they have no evidence, and they have to get the number of people in the discussion down to as small as possible.

In REAL science, the more people involved the better because everyone will have a different perspective and you gain the knowledge of everyone instead of a few people. The more people, the more likely to catch mistakes and errors. Yet crackpot groups like PFT have goals of trying to reduce the number of people in discussion to as few as possible. Again, the less people to correct or point out problems the better for them. This goes against scientific principle and is not research. It's a witch hunt.

 

[R.Mackey]

Yup, I'm losing bad...I'm not the one who hasn't returned in weeks with a frame
layout to support a theory (Anti)...I am not the one declining public debate
and willing to put my name on the line (everyone here, except Caustic Logic).

This is part of why it's so hard to take you seriously. Out of you and I, it is I who has "put my name on the line," not you. And your attempts to move the discussion out of public view, to a private telephone conversation, are hardly a move towards transparency.

If you have something to say, say it here. You've posted over 700 times. Surely you've got the hang of it.

Furthermore, this method is superior than a phone conversation. For example: Today I ran by our library over lunch and collected some information on EEPROM and Flash faults outside normal operations. Here's three excerpts:

During write and erase cycling, hole injection into the tunnel dielectric has been shown to be responsible for an increase in the width of the erase distribution. Over-erasure can subsequently occur, which leads to depleted bits. Simulations were performed to identify the necessary hole density and spatial location to create enhanced tunneling, which would result in bits with erratic erase. These simulations indicated that one major factor which can reduce the impact of the trapped holes is an increase in the field across the tunnel during erase.

Source: C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, T. San, all of Texas Instruments, "Flash EPROM Disturb Mechanisms," in Proceedings of the 32nd International Reliability Physics Symposium, April 12-14, 1994, San Jose, California.

This excerpt refers to damage caused by flaky operation during low voltage. "Depleted Bits" are those that are excessively "erased" and become harder to charge during a write operation, leading to entire blocks of unreliable Flash memory. This is one of three physical mechanisms described in this paper, which quantifies rate of failure as a function of several quantities, including source and wordline voltage and temperature.

The HMOS disturbs are evaluated first. A program disturb can occur for cells on the same select-line with V_pg = 9 V, as it is possible that electrons might tunnel onto the floating gate. In the V_t(LO) (erased) state, ΔV_fg due to Q_fg is positive and with V_pg capacitively coupled also, FN tunnelling could take place from the channel. For cells on the same bit line, leakage current is a concern. In the V_t(LO) state the floating gate part of the channel is on, and with V_d = 3.3 V, I_leak will flow and will become a bigger problem if L_cgate is scaled. Again, for cells on the same bit-line V_d = 3.3V, BBT will take place near the drain junction edge. The worst case occurs when a floating gate is in the programmed state (V_t(HI)).

[...] Another disturb is possible due to a punchthrough effect. If there is a defect that reduces channel length and creates a punchthrough path, hot carriers might be generated to program an erased cell.

Source: R. Duffy, A. Concannon, A. Mathewson, B. Lane, "Scaling embedded EEPROMs for the integration [sic] in deep submicron technologies," Microelectronics (Elsevier), Vol. 32 (2001), pp. 35-42.

As it turns out there are multiple mechanisms for affecting nearby cells. The standard parasitic effects when voltage accidentally increases, and the "punchthrough" effect which is actual electron tunneling. I hadn't known the latter was practical at levels low enough to prevent straight up burnout, but there it is. Regarding punchthrough, this article specifically discusses manufacturing defects that lower the tunneling voltage, but a rise in voltage will similarly result in tunneling.

Three sets of faults can be identified, depending on the localization of the bridge resistance. The first set includes the intra-cell faults, the second set includes the inter-cell faults, and the third the array faults. These sets are defined respectively as follows:

• The intra-cell faults are the bridging faults between two internal nodes of a same cell or between an internal node and an external node of a same cell [sic]. [...]

• The inter-cell faults are the bridging faults between an internal node of a cell and an external or internal node of an adjacent cell. [...]

• The array faults are the bridging faults between two nets of the array illustrated in Figure 1.a. [...]

Source: J. Portal, A. Perez, "Analyzing Bridging Faults Impact on EEPROM Cell Array," Proceedings of the 2001 IEEE European Test Workshop, pp. 3-8, May 29-June 1, 2001, Stockholm, Sweden.

This paper describes an experiment using a simple 2x2 array, in which bridging faults are forced to occur through different combinations of initial state and, drum roll please, out-of-spec voltages. Bridging faults refer again to defects in manufacturing, and typically the manufacturer's QA process will reject the bad ones -- but this QA is done at nominal operating voltages. Bridging resistances are always there, just normally too high to affect normal operation. But if you put a transient on the chip, the bridge may flow enough current to corrupt the data.


This I found in 20 minutes, less time than it took to transcribe it here. I haven't even notified the heavy guns yet. The bottom line is that data corruption in EEPROM and Flash is possible, primarily due to faults in the power system, such as can be expected during a ruddy plane crash. This is why data has to be carefully analyzed by hand.

And again, this is one possible explanation of what happened to the last few seconds of FDR data.

Back to you, Turbofan.

 

[Turbofan]

TF, so far various persons in this thread have found multiple instances of reported corrupted or lost data from EEPROMs due to voltage fluctuations. Only your bald assertion that this cannot happen backs up your contention that it does not occur in the specific EEPROM that the FDR used.

Also posted here are several instances in which data on an FDR indicates a loss of several seconds worth of data at the end of the flight which also would indicate that your premise, of the infallibility of the last frames of data in a crash situation, is incorrect.
Will one find a senario that exactly matches what occured to flight 77? No, not likely since it is very very unusual for an aircraft at cruise speed or greater, with no control or powering problems to impact the ground , much less concrete buildings, while in controlled flight.

It certainly looks like you are back pedaling and avoiding posting links to your electronic forum threads, and it is well noted that as soon as people started calling for those links that you bring up another subject, that of the entry and exit holes sizes and shapes. Which , BTW, I agree with the others that a discussion of that belongs in a thread on that subject. Seems to me that you are quick to point out that this is an FDR thread when someone asks you about where Flight 77 and its passengers went.

Na, don't go there buddy. It's not at all like you've said.

There is no example here of single bits overwriting previously recorded data.

I do admit the current write access may corrupt the active address, however
six seconds worth of data requires several clock cycles and six seconds worth
of power to be wiped out. EEPROM = Electrical erase...not impact, or whatever
is floating around here.

Point 2. There are no examples of aircraft that lost data in the form that
AA77 'presumably" lost data. The only examples I have seen here are
plane that have lost power mid flight and crashed at a later time.

This is NOT the same scenario for our example.

Why don't you guys sign up at some engineering forums and I'll do the same?
Maybe you can take some time out of your busy schedules like myself.
YOu'll get the links when I'm ready and have time. Until then, go watch TV
or whatever you do best.

Maybe you can send a few PM's to R. Mackey and beg him to sit on the
phone live with PFT. He is your most vocal member, and one that you all
follow most. Get your 'leader' out of internet land on radio where he can
be heard.

 

[Turbofan]

Again, for cells on the same bit-line Vd = 3.3V, BBT will take place near the drain junction edge. The worst case occurs when a floating gate is in the programmed state (Vt(HI)).

"Depleted Bits" are those that are excessively "erased" and become harder to charge during a write operation, leading to entire blocks of unreliable Flash memory

This paper describes an experiment using a simple 2x2 array, in which bridging faults are forced to occur through different combinations of initial state and, drum roll please, out-of-spec voltages.

Do you even know what you're reading? Maybe you should consult your
big guns and get them out here (please!).

I don't see any mention of transient duration, voltage/second, or SINGLE BIT
ACCESS in the quotes taken from your library books!

Do you see that bolded section up there that say BLOCKS!? If you apply
a voltage to a parallel line, what happens to all components connected
to that line?

Drum roll please....

All connected components are effected! Voltage is common in a parallel
circuit. Did you forget that part of Ohms Law in Engineering school...
or is it that you're not an electrical/electronics engineer?

 

[R.Mackey]

Your objections are incoherent. Please try reading more carefully.

I gave you the references, in case you want to check yourself. Not sure what else I can be expected to do at this juncture.

 

[Turbofan]

Again, for cells on the same bit-line Vd = 3.3V, BBT will take place near the drain junction edge. The worst case occurs when a floating gate is in the programmed state (Vt(HI)).

"Depleted Bits" are those that are excessively "erased" and become harder to charge during a write operation, leading to entire blocks of unreliable Flash memory

This paper describes an experiment using a simple 2x2 array, in which bridging faults are forced to occur through different combinations of initial state and, drum roll please, out-of-spec voltages.

Do you even know what you're reading? Maybe you should consult your
big guns and get them out here (please!).

I don't see any mention of transient duration, voltage/second, or SINGLE BIT
ACCESS in the quotes taken from your library books!

Do you see that bolded section up there that says BLOCKS!? If you apply
a voltage to a parallel line, what happens to all components connected
to that line?

Drum roll please....

All connected components are effected! Voltage is common in a parallel
circuit. Did you forget that part of Ohms Law in Engineering school...
or is it that you're not an electrical/electronics engineer?

Please provide the necessary transient voltage and duration needed to wipe
out six seconds worth of data.

After you do that, please explain how the FDR retained that amount of
power after "impact". Remember, you even specified 200 msec MAX.

Also give me the block size for the memory chip used in AA77's FDR.
I'll give you a hint, Undertow has the part number and specs. It's also
linked within this thread (hurry and find it before I delete it )

Go ahead Mr. Mackey, give me your best shot. Get your big guns out here to
help out. I'll get mine if needed.

 

[R.Mackey]

Please provide the necessary transient voltage and duration needed to wipe
out six seconds worth of data.

After you do that, please explain how the FDR retained that amount of
power after "impact". Remember, you even specified 200 msec MAX.

Go ahead Mr. Mackey, give me your best shot. Get your big guns out here to
help out. I'll get mine if needed.

I already told you this. You can wipe out six seconds of data with a mere two bits, if you hit the right ones. Corruption is the issue, not an orderly erase cycle.

Higher voltage is possible because of arcing in the power system. There is also the possibility of static discharge if the memory module physically moves during collision, which I discount, but anything is possible in a crash of that severity. As for duration, we're talking nanoseconds here. That's all that is needed under some situations.

So far, you do not appear to be even capable of understanding what I wrote. I'm afraid the burden of proof remains upon you until that situation changes.

 

[WildCat]

Why don't you guys sign up at some engineering forums and I'll do the same?

You're the one who was so confident that you promised to post mackey's quotes on an engineering forum to show how wrong he is. I see now you're running away from your claim like a scared little schoolgirl. I'm sure real engineers don't want their forum tainted by truther nonsense, so you'll likely have to do it all by yourself.

Maybe you can take some time out of your busy schedules like myself.

You're the one who promised to post on an engineering forum, now you have chickened out I see.

YOu'll get the links when I'm ready and have time. Until then, go watch TV
or whatever you do best.

Your multiple posts here since your promise shows you have the time. And besides, it shouldn't take you long since your case is such a slam dunk, right?

Maybe you can send a few PM's to R. Mackey and beg him to sit on the
phone live with PFT. He is your most vocal member, and one that you all
follow most. Get your 'leader' out of internet land on radio where he can
be heard.

One thing is abundantly clear - the PfffT and you avoid corroborating your moronic conclusions with actual FDR experts because you know damn well none will agree with them.

Meanwhile, the optimist I am, I'll keep bumping the thread created for you to post your links. Either you follow through and embarrass yourself when real electronic engineers side with Mackey, or you ignore it and expose yourself for the cowardly fraud you are. Tough choice, isn't it?

Of course, you could always leave this site entirely and pretend you were never here...

 

[Turbofan]

I already told you this. You can wipe out six seconds of data with a mere two bits, if you hit the right ones. Corruption is the issue, not an orderly erase cycle.

I already told you this: if you apply a voltage to a line which connects
several components, they are all effected. It doesn't matter if it's static,
arc, or intentional.

You see there are hundreds of thousands, if not millions of these gates
within the IC. Do you think there are 100,000 address lines? You did look
at the schematic...right? if you hit one, you hit MANY on the same address line.

So far, you do not appear to be even capable of understanding what I wrote. I'm afraid the burden of proof remains upon you until that situation changes.

When you can give me a basic understanding of Ohm's Law, I'll let you get
away with such an incorrect statement.

Am I allowed to hot link that EEPROM layout, or will I get a warning? This
will be from my FTP server.

 

[R.Mackey]

I gave you a factual answer. You are blowing smoke.

This is why nobody wants to "debate" you. Can you imagine this kind of exchange on a radio show? Even Jerry Springer has higher standards.

 

[Turbofan]

I gave you a factual answer. You are blowing smoke.

This is why nobody wants to "debate" you. Can you imagine this kind of exchange on a radio show? Even Jerry Springer has higher standards.

You gave me a theory which is incorrect and falls short of Ohm's Law.

You're scared to get on the phone, or speak on radio because I would
nail you to the wall at the word, "Hello, I'm R. Mac..."

Parallel Circuits:

http://www.tpub.com/neets/book1/chapter3/1-24.htm

IN A PARALLEL CIRCUIT, THE SAME VOLTAGE IS PRESENT IN EACH BRANCH. (A branch is a section of a circuit that has a complete path for current.) In figure 3-37 this voltage is equal to the applied voltage (Es). This can be expressed in equation form as:

ES = ER1 = ER2

This very same concept applies within the EEPROM where all gates are tied
together by address lines (these lines are common). Each single gate DOES
NOT have it's own address line!

 

[beachnut]

You gave me a theory which is incorrect and falls short of Ohm's Law.

You're scared to get on the phone, or speak on radio because I would
nail you to the wall at the word, "Hello, I'm R. Mac..."

Parallel Circuits:

http://www.tpub.com/neets/book1/chapter3/1-24.htm



This very same concept applies within the EEPROM where all gates are tied
together by address lines (these lines are common). Each single gate DOES
NOT have it's own address line!

Turbofan - Waves hands, declares it wrong…

Mackey is winning by an order of magnitude

I am an electrical engineer, Turbofan, you are doing very poorly

Round 1 Mackey - carry on

 

[R.Mackey]

You gave me a theory which is incorrect and falls short of Ohm's Law.

You're scared to get on the phone, or speak on radio because I would
nail you to the wall at the word, "Hello, I'm R. Mac..."

Let me get this straight. You claim you can reject out of hand, among other things, a published, refereed article written by three Ph.D's from Microelectronics Journal, because it violates Ohm's Law.

And you think I'm "afraid" because I think you're smarter than I am.

Here's a suggestion. Why don't you add this little detail to those posts you're supposedly making on EE forums? And please let me know how that goes for you.

 

[DavidJames]

TurboFan - by my count it's been 36 hours since you posted that you had registered at "all of the EE forums" and alluded to posting Ryan's comments. You've repeatedly been asked to provide links, you've refused.

Why?

I'm also wondering what happened to the moderated debate you requested. The last post had the mod asking you present your opening argument. Since you may have submitted your argument and it is being reviewed, I will refrain from calling you out on it. Have you submitted your argument?

 

[Jonnyclueless]

Why is turbo not able to nail Mackey here, but he supposedly could on the phone. Is there some magical properties of a phone that prevent him from doing it here? What is Turbo witholding here that he could present over the phone and why is he witholding?

 

[jaydeehess]

I got my electronics diploma in 1984 when EPROMs still required baking in UV to erase them and yet,,, I understood the references Mackey gave in which it is outlined that transients can cause quantum effects that corrupt data in cells or blocks adjacent to ones being written to or being erased.

I suggest that TF re-read the quotes, especially C.Dunn at al, or better yet go and see if he can get the same book.

Then again I suppose Ph.D.'s in electrical engineering might get it wrong and TF is correct in assuming the infallability of the last few recorded frames of data.

 

[jaydeehess]

I already told you this: if you apply a voltage to a line which connects
several components, they are all effected. It doesn't matter if it's static,
arc, or intentional.

Oh it indeed does matter. A high voltage very fast transient will affect individual circuits depending on the variations in bridging resistance and impedance of that cell and the source path for that transient and the physical distance to the individual cells.

This is why lightning can do some very odd things.

You see there are hundreds of thousands, if not millions of these gates
within the IC. Do you think there are 100,000 address lines? You did look
at the schematic...right? if you hit one, you hit MANY on the same address line

But when the spike occurs data is being written to certain cells , which in turn are physically closer to the cells that have just been written to than others in the array. Punchthrough and tunneling will occur there, not further away. Again, this take nanoseconds.

When you can give me a basic understanding of Ohm's Law, I'll let you get
away with such an incorrect statement.

That you cannot grasp that this goes beyond Ohm's steady state conditions is revealing.

For what its worth;
voltage accross an element is equal to the current through that element multiplied by the electrical resisitance of that element
V=IR

A simple example of where Ohm's does not apply is in charging a capacitor. By Ohm's Law the current through it (in a dc cct) is zero since we can assume the cap to have a sufficiently high resistance. However since it takes time to charge the cap, current actually does flow!

Do you recall the mnemonic;
ELI ICE ?

 

[Turbofan]

Oh please, will all of the electronic and electrical pros please step up to
the plate and explain how one single gate is effected, but the other ones
attached to the same address line are not?

How can you not wipe out entire blocks as opposed to six seconds worth?

When address lines are enabled and a certain bit is going through the write
stage, any current flow is shunted down the active gate if the bit line goes
'low' (to change the current bit to a zero state).

Those who know the terminology refer to this as forward biased.

The 'gate' is closed and therefore no potential difference (*aside from
internal resistance being very little) can be measured across the junction.
Read value = 0 (<= 10% of VCC).

All other gates connected to this address line at a "one" state remain
unchanged because their current path is 'open' (not biased for current flow).
If you measure the potential difference across this gate, you will see a
voltage of significance (>=70% of VCC).

If a transient , arc, or static discharge targeted a gate in a "one" state,
that voltage would be shared with all other gates on that line. Therefore,
if you have enough potential voltage to change the state of one gate, you
have the potential voltage to change all gates on that address line.
VOltage is shared in a parllel circuit.

The transient cannot single out just one, or two bits (gates). The transient
would change several thousand gates effectively wiping out an entire block
of data.

 

[WildCat]

Oh please, will all of the electronic and electrical pros please step up to
the plate

Speaking of stepping up to the plate... http://www.internationalskeptics.com/forums/showthread.php?t=124431

 

[jaydeehess]

So you prove the authors of the texts Mackey cites wrong then? IS that what you are saying?

You do understand what they are saying, right?